(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a self-aligned elevated transistor using the technique of silicon epitaxial growth in the manufacture of integrated circuits.
(2) Description of the Prior Art
Shallow trench isolation (STI) will be employed widely in current and future integrated circuit technologies to provide sufficient isolation between neighboring devices. However, there are a number of problematic issues in STI processes including "hump effects" and chemical mechanical polishing (CMP) induced dishing over wide trenches that must be resolved prior to its further and wider applications. The STI corner represents an abrupt transition from the transistor active area to isolation. The gate polysilicon wraparound of a sharp trench corner causes a separate conduction characteristic of the corner resulting in a "double hump" in the transistor drain current-gate voltage characteristics. It is desired to void the problem of the "hump effects." Another problem with STI processes is that the packing density of integrated circuits will be limited by the dimensions of the isolation trenches. It is desired to fabricate an integrated circuit without the drawbacks of the STI process.
U.S. Pat. No. 4,749,441 to Christenson et al teaches a method of selective epitaxial growth (SEG) to form elevated source/drain regions. However, the gate electrode is not formed by self-aligning techniques. U.S. Pat. No. 5,686,343 to Lee teaches forming an epitaxial layer and patterning it to provide an active area. U.S. Pat. No. 5,780,343 discloses the formation of an SEG layer within a trench and forming a gate thereover. U.S. Pat. No. 5,681,776 to Hebert et al teaches SEG within a trench and then oxidation of the SEG regions to form trench isolation. U.S. Pat. No. 5,453,396 to Gonzalez et al discloses a SEG process for a DRAM.